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S72NS-P Based MCPs/PoPs
MirrorBitTM Flash Memory and DRAM 128/256/512 Mb (8/16/32 M x 16 bit), 1.8 Volt-only, Multiplexed Simultaneous Read/Write, Burst Mode Flash Memory 128/256 Mb (8/16 M x 16 bit) DDR DRAM on Split Bus
Data Sheet (Advance Information)
S72NS-P Based MCPs/PoPs Cover Sheet
Notice to Readers: This document states the current technical specifications regarding the Spansion product(s) described herein. Each product described herein may be designated as Advance Information, Preliminary, or Full Production. See Notice On Data Sheet Designations for definitions.
Publication Number S72NS-P_00
Revision 01
Issue Date September 6, 2006
Data
Sheet
(Advance
Information)
Notice On Data Sheet Designations
Spansion Inc. issues data sheets with Advance Information or Preliminary designations to advise readers of product information or intended specifications throughout the product life cycle, including development, qualification, initial production, and full production. In all cases, however, readers are encouraged to verify that they have the latest information before finalizing their design. The following descriptions of Spansion data sheet designations are presented here to highlight their presence and definitions.
Advance Information
The Advance Information designation indicates that Spansion Inc. is developing one or more specific products, but has not committed any design to production. Information presented in a document with this designation is likely to change, and in some cases, development on the product may discontinue. Spansion Inc. therefore places the following conditions upon Advance Information content:
"This document contains information on one or more products under development at Spansion Inc. The information is intended to help you evaluate this product. Do not design in this product without contacting the factory. Spansion Inc. reserves the right to change or discontinue work on this proposed product without notice."
Preliminary
The Preliminary designation indicates that the product development has progressed such that a commitment to production has taken place. This designation covers several aspects of the product life cycle, including product qualification, initial production, and the subsequent phases in the manufacturing process that occur before full production is achieved. Changes to the technical specifications presented in a Preliminary document should be expected while keeping these aspects of production under consideration. Spansion places the following conditions upon Preliminary content:
"This document states the current technical specifications regarding the Spansion product(s) described herein. The Preliminary status of this document indicates that product qualification has been completed, and that initial production has begun. Due to the phases of the manufacturing process that require maintaining efficiency and quality, this document may be revised by subsequent versions or modifications due to changes in technical specifications."
Combination
Some data sheets contain a combination of products with different designations (Advance Information, Preliminary, or Full Production). This type of document distinguishes these products and their designations wherever necessary, typically on the first page, the ordering information page, and pages with the DC Characteristics table and the AC Erase and Program table (in the table notes). The disclaimer on the first page refers the reader to the notice on this page.
Full Production (No Designation on Document)
When a product has been in production for a period of time such that no changes or only nominal changes are expected, the Preliminary designation is removed from the data sheet. Nominal changes may include those affecting the number of ordering part numbers available, such as the addition or deletion of a speed option, temperature range, package type, or VIO range. Changes may also include those needed to clarify a description or to correct a typographical error or incorrect specification. Spansion Inc. applies the following conditions to documents in this category:
"This document states the current technical specifications regarding the Spansion product(s) described herein. Spansion Inc. deems the products to have been in sufficient production volume such that subsequent versions of this document are not expected to change. However, typographical or specification corrections, or modifications to the valid combinations offered may occur."
Questions regarding these document designations may be directed to your local Spansion sales office.
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S72NS-P Based MCPs/PoPs
September 6, 2006 S72NS-P_00-01
S72NS-P Based MCPs/PoPs
MirrorBitTM Flash Memory and DRAM 128/256/512 Mb (8/16/32 M x 16 bit), 1.8 Volt-only, Multiplexed Simultaneous Read/Write, Burst Mode Flash Memory 128/256 Mb (8/16 M x 16 bit) DDR DRAM on Split Bus
Data Sheet (Advance Information)
Features
Power supply voltage of 1.7 V to 1.95 V Burst Speeds
- Flash = 66 MHz, 80 MHz - DRAM = 133 MHz
Packages
- 11.0 x 10.0 mm, 133-ball MCP - 8.0 x 8.0 mm, 133-ball MCP - 12.0 x 12.0 mm, 128-ball PoP
Operating Temperature of -25C to +85C
General Description
This document contains information on the S72NS-P MCP stacked products. Refer to the S29NS-P data sheet (S29NS-P_00) for full electrical specifications of the Flash memory component. The S72NS Series is a product line of stacked products (MCPs and PoPs), and consists of: NS family multiplexed Flash memory die DDR DRAM The products covered by this document are listed in the tables below.
DRAM Density Flash Density 128 Mb 256 Mb 512 Mb 128 Mb S72NS128PD0 S72NS256PD0 S72NS512PD0 S72NS512PE0 256 Mb
For detailed specifications, please refer to the individual data sheets.
Density 128 DRAM5 SDRAM_07 Manufacturer DRAM1 Publication Number SDRAM_03
Density 256
Manufacturer DRAM1 DRAM5
Publication Number TBD SDRAM_11
Publication Number S72NS-P_00
Revision 01
Issue Date September 6, 2006
This document contains information on one or more products under development at Spansion Inc. The information is intended to help you evaluate this product. Do not design in this product without contacting the factory. Spansion Inc. reserves the right to change or discontinue work on this proposed product without notice.
Data
Sheet
(Advance
Information)
1.
Product Selector Guide
Device OPN S72NS128PD0AJBGG S72NS128PD0AJBGC 128 Mb S72NS128PD0AJBLG S72NS128PD0AJBLC S72NS128PD0KJFGG S72NS128PD0KJFGC 128 Mb S72NS128PD0KJFLG S72NS128PD0KJFLC S72NS256PD0AJBGG S72NS256PD0AJBGC 256 Mb S72NS256PD0AJBLG S72NS256PD0AJBLC S72NS256PD0KJFGG S72NS256PD0KJFGC 256 Mb S72NS256PD0KJFLG S72NS256PD0KJFLC S72NS512PD0AJGGG S72NS512PD0AJGGC 512 Mb S72NS512PD0AJGLG S72NS512PD0AJGLC S72NS512PD0KJFGG S72NS512PD0KJFGC 512 Mb S72NS512PD0KJFLG S72NS512PD0KJFLC S72NS512PE0AJGGG S72NS512PE0AJGGC 512 Mb S72NS512PE0AJGLG S72NS512PE0AJGLC S72NS512PE0KJFGG S72NS512PE0KJFGC 512 Mb S72NS512PE0KJFLG S72NS512PE0KJFLC 256 Mb 66 DRAM5 80 256 Mb 66 DRAM5 80 66 DRAM1 80 133 12.0 x 12.0mm 128-ball PoP 128 Mb 66 DRAM5 80 66 DRAM1 80 133 11.0 x 10.0mm 133-ball MCP 128 Mb 66 DRAM5 80 66 DRAM1 80 133 12.0 x 12.0mm 128-ball PoP 128 Mb 66 DRAM5 80 66 DRAM1 80 133 11.0 x 10.0mm 133-ball MCP 128 Mb 66 DRAM5 80 66 DRAM1 80 133 12.0 x 12.0mm 128-ball PoP 128 Mb 66 DRAM5 80 66 DRAM1 80 133 8.0 x 8.0mm133-ball MCP 128 Mb 66 DRAM5 80 66 DRAM1 80 133 12.0 x 12.0mm 128-ball PoP Flash Density DDR DRAM Density Flash Speed (MHz) 66 DRAM1 80 133 8.0 x 8.0mm133-ball MCP DDR DRAM Speed (MHz) Supplier Package
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Data
Sheet
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Information)
2. Product Block Diagram
F-RST# F-ACC F-WP# F-CE# F-OE# F-WE# AVD# F-VSS F2-CE#
RST# ACC WP# CE# OE# WE# AVD# VSS
A15-A0 DQ15-DQ0
ADQ15-ADQ0
MUX Flash Memory NS-P
CLK RDY
F-CLK F-RDY
Amax - A16 VCC VCCQ
Amax - A16 F-VCC F-VCCQ
D-RAS# D-CAS# D-BA0 D-BA1 D-CKE D-WE# D-CE# D-Amax - D-A0 D-VCC D-VCCQ
RAS# CAS# BA0 BA1 CKE WE# CE#
CLK CLK# DQS0 DQS1
D-CLK D-CLK# D-LDQS D-UDQS D-LDQM D-UDQM D-TEST D-DQ15 - D-DQ0 D-VSS D-VSSQ
DDR DRAM Memory
LDQM UDQM TEST DQ15-DQ0 VSS VSSQ
VCC VCCQ
Notes: 1. Amax indicates highest address bit for memory component: a. Amax = A24 for NS512P, A23 for NS256P, A22 for NS128P b. Amax = A11 for 128 Mb DDR DRAM c. Amax = A12 for 256Mb DDR DRAM 2. For Flash, A15 - A0 is tied to DQ15 - DQ0.
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Data
Sheet
(Advance
Information)
3. Connection Diagrams
Figure 3.1 133-ball Fine-Pitch Ball Grid Array MCP
1 A DNU B DNU C D-VCC D-DQ15 D-DQ14 D-DQ12 D-DQ11 D-UDQM D-VSS D-VCC D-VSSQ D-DQ7 D-LDQS D-DQ2 D-DQ0 D-VSS No Connect D RFU E A24 F A23 G F-CE# H F-ACC J A16 K A21 L A20 M NC N DNU P DNU DNU NC D-A4 D-A7 D-RAS# D-CLK D-VCC D-BA0 D-A0 D-VCC D-VSS DNU DNU D-VSS D-VCC D-A5 D-A8 D-CAS# D-CLK# D-BA1 D-A11 D-A2 D-A12 NC F-VCC DNU NC D-A3 D-A6 D-A9 D-CKE D-VSS D-WE# D-A10 D-A1 NC NC F-RDY F-VSS F-RST# D-CE# F-VCCQ ADQ15 ADQ14 F-AVD# NC NC ADQ7 ADQ6 F-VSS NC F-VSS F-VSS ADQ5 F-VCC F-CLK ADQ13 ADQ12 ADQ4 F-WP# F-WE# F-VCCQ ADQ11 ADQ10 A19 A18 F-VSS ADQ3 ADQ2 Reserved for Future Use A22 A17 ADQ9 ADQ1 ADQ0 Code Flash Only NC NC INDEX F-OE# ADQ8 D-VCC DRAM Only D-VSS D-DQ13 D-UDQS D-DQ10 D-VSSQ D-VCCQ D-VCCQ D-LDQM D-DQ6 D-DQ4 D-DQ1 D-VCCQ DNU Do Not Use DNU D-VSSQ D-VCCQ D-DQ9 D-DQ8 D-VSS D-VCC D-VCC D-DQ5 D-DQ3 D-VSSQ DNU DNU Index Location 2 3 4 5 6 7 8 9 10 11 12 13 14 Legend
Note: Additional NC locations are in reference to the superset connection diagram shown here
Device OPN S72NS128PD0 S72NS256PD0 S72NS512PD0 S72NS512PE0
Flash Address Amax A22 A23 A24 A24
DDR DRAM Address Amax A11 A11 A11 A12
Additional NC Locations Ball F1, Ball E1, Ball N11 Ball E1, Ball N11 Ball N11 N/A
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Figure 3.2 128-ball Fine-Pitch Ball Grid Array, PoP
1 A NC B NC C F-AVD# F-OE# D F-RST# F-RDY E F-VCCQ F-WE# F F-VCCQ F-VSS G F-VSS H F-VSS J F-VSS K A23 L A20 M A21 N F-ACC P F-VCC R A17 T NC U F-WP# V NC NC NC NC D-VCC D-VCC D-A2 D-A0 D-BA1 D-BA0 D-VSS D-VSS NC D-A8 D-RAS# D-A6 D-A4 NC NC NC NC D-CE# D-A3 D-A1 D-A10 D-CKE D-A12 D-A11 D-WE# D-A9 D-A7 D-CAS# D-A5 NC D-VSS A24 D-VCC D-VSSQ A22 D-VCCQ D-VSSQ F-VCC D-DQ0 D-LDQS A19 D-DQ2 D-DQ1 A16 D-DQ4 D-DQ3 A18 D-DQ6 D-DQ5 F1-CE# LDQM D-DQ07 F-VSS D-CLK D-CLK# F-VSS D-DQ8 D-UDQM F-VSS D-DQ9 D-DQ10 D-DQ11 D-DQ12 D-DQ13 D-DQ14 D-UDQS D-DQ15 D-VSSQ D-VSSQ DDR DRAM Only NC ADQ0 ADQ1 ADQ2 ADQ3 ADQ4 ADQ5 ADQ6 ADQ7 F-CLK D-VSS D-VCCQ D-VCCQ D-VCCQ D-VCC NC D-VSSQ NOR Flash Only NC ADQ8 ADQ9 ADQ10 ADQ11 ADQ12 ADQ13 ADQ14 ADQ15 D-VSS D-VSS D-VCCQ D-VCCQ D-VCC D-VCC D-VSSQ NC NO Connect 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 Legend
Note: Additional NC locations are in reference to the superset connection diagram shown here.
Device OPN S72NS128PD0 S72NS256PD0 S72NS512PD0 S72NS512PE0
Flash Address Amax A22 A23 A24 A24
DDR DRAM Address Amax A11 A11 A11 A12
Additional NC Locations Ball K1, Ball T2, Ball U10 Ball K1, Ball U10 Ball U10 N/A
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Data
Sheet
(Advance
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4.
Input/Output Descriptions
Signal Amax - A16 ADQ15 - ADQ0 F-CE# F-OE# F-WE# F-VCC F-VCCQ F-VSS F-RDY = = = = = = = = = = F-CLK Flash Address inputs Flash multiplexed Address and Data Flash Chip-enable input. Asynchronous relative to CLK for Burst Mode Flash Output Enable input. Asynchronous relative to CLK for Burst mode. Flash Write Enable input Flash device power supply (1.7 V to 1.95 V) Flash Input/Output Buffer power supply Flash Ground Flash ready output. Indicates the status of the Burst read. VOL = data invalid. VOH = data valid. Flash Clock. The first rising edge of CLK in conjunction with AVD# low latches the address input and activates burst mode operation. After the initial word is output, subsequent rising edges of CLK increment the internal address counter. CLK should remain low during asynchronous access. Flash Address Valid input. Indicates to device that the valid address is present on the address inputs. VIL = for asynchronous mode, indicates valid address; for burst mode, causes starting address to be latched on rising edge of CLK. VIH= device ignores address inputs Flash hardware reset input. VIL= device resets and returns to reading array data Flash hardware write protect input. VIL = disables program and erase functions in the four outermost sectors Flash accelerated input. At VHH, accelerates programming; automatically places device in unlock bypass mode. At VIL, disables all program and erase functions. Should be at VIH for all other conditions. DRAM Address inputs. DRAM Data input/output DRAM System Clock DRAM Chip Select DRAM Clock Enable DRAM Bank Select DRAM Row Address Strobe DRAM Column Address Strobe DRAM Data Input Mask DRAM Write Enable input DRAM Ground DRAM Input/Output Buffer ground DRAM Input/Output Buffer power supply DRAM device power supply DRAM Upper Data Strobe, output with read data and input with write data DRAM Lower Data Strobe, output with read data and input with write data DDR Clock for negative edge of CLK Reserved for Future Use No Connect. Can be connected to ground or left floating. Do Not Use. This signal must be left floating X X X X X X X Description Flash DRAM
X
= F-AVD#
X
F-RST# F-WP#
= = =
X X
F-ACC D-A12 - D-A0 D-DQ15 - D-DQ0 D-CLK D-CE# D-CKE D-BA1 - BA0 D-RAS# D-CAS# D-UDQM - D-LDQM D-WE# D-VSS D-VSSQ D-VCCQ D-VCC D-UDQS D-LDQS D-CLK# RFU NC DNU = = = = = = = = = = = = = = = = = = = =
X X X X X X X X X X X X X X X X X X
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Sheet
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Information)
5.
Ordering Information
The order number (Valid Combination) is formed by the following:
256 P D0 AJ B L G 3 PACKING TYPE 0 = Tray 2 = 7-inch Tape and Reel 3 = 13-inch Tape and Reel FLASH and DDR SPEED G = 66 MHz Flash, 133 MHz DDR DRAM C = 80 MHz Flash, 133 MHz DDR DRAM DDR SUPPLIER G = DRAM Type 1 x16 DDR DRAM L = DRAM Type 5 x16 DDR DRAM PACKAGE MODIFIER G = 133-ball, 11x10mm, FBGA MCP B = 133-ball, 8x8mm, FBGA MCP F = 128-ball, 12x12mm, FBGA PoP PACKAGE AND MATERIAL TYPE AJ = Thin profile Fine-pitch BGA Pb-free LF35 MCP (0.5 mm pitch) KJ = Thin profile Fine-pitch BGA Pb-free PoP (0.65 mm pitch) DDR DRAM AND DATA FLASH DENSITY D0 = 128 Mb DRAM, No Data Flash E0 = 256 Mb DRAM, No Data Flash PROCESS TECHNOLOGY P = 90 nm, MirrorBitTM Technology CODE FLASH DENSITY 512 = 512 Mb 256 = 256 Mb 128 = 128 Mb PRODUCT FAMILY S72NS Multi-Chip Product (MCP) 1.8 V Multiplexed, SRW, Burst Mode Flash and DDR DRAM on Split Bus
S72NS
Valid Combinations Product Family Code Flash Density (Mb) 128 D0 S72NS 256 512 Notes: 1. Packing Type 0 is standard. Specify other options as required. 2. BGA package marking omits leading "S" and packing type designator from ordering part number. 3. Valid Combinations list configurations planned to be supported in volume for this device. Consult your local sales office to confirm availability of specific valid combinations and to check on newly released combinations. P D0, E0 AJG, KJF AJB, KJF G, L G, C Process Technology DRAM Density (Mb) Package Type/ Material Flash & DDR Speed G, C 0, 2, 3 (Note 1) Packing Type
DDR Vendor
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Data
Sheet
(Advance
Information)
6.
6.1
Physical Dimensions
NLC133--133-ball Fine-Pitch Ball Grid Array (FBGA) 11.0 x 10.0 mm
NOTES: PACKAGE JEDEC DxE SYMBOL A A1 A2 D E D1 E1 MD ME n Ob eE eD SD / SE 0.25 NLC 133 N/A 11.0 mm x 10.00 mm PACKAGE MIN 0.90 0.20 0.70 10.9 9.9 NOM 1.00 0.25 0.76 11.0 10.0 6.50 BSC. 6.50 BSC. 14 14 133 0.30 0.50 BSC. 0.50 BSC 0.25 BSC. D5-D11, E4-E11, F4-F11 G4-G11, H4-H11, J4-J11 K4-K11, L4-L11 0.35 MAX 1.10 0.30 0.82 11.1 10.1 PROFILE BALL HEIGHT BODY THICKNESS BODY SIZE BODY SIZE MATRIX FOOTPRINT MATRIX FOOTPRINT MATRIX SIZE D DIRECTION MATRIX SIZE E DIRECTION BALL COUNT BALL DIAMETER BALL PITCH BALL PITCH SOLDER BALL PLACEMENT DEPOPULATED SOLDER BALLS 9. 8. 7 6 NOTE 2. 3. 4. 5. 1. DIMENSIONING AND TOLERANCING METHODS PER ASME Y14.5M-1994. ALL DIMENSIONS ARE IN MILLIMETERS. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010. e REPRESENTS THE SOLDER BALL GRID PITCH. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D" DIRECTION. SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE "E" DIRECTION. n IS THE NUMBER OF POPULTED SOLDER BALL POSITIONS FOR MATRIX SIZE MD X ME. DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL DIAMETER IN A PLANE PARALLEL TO DATUM C. SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A AND B AND DEFINE THE POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW. WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE OUTER ROW SD OR SE = 0.000. WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW, SD OR SE = e/2 "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED BALLS. N/A
10 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.
3436 \ 16-039.22 \ 12.09.04
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6.2
NSC133--133-ball Fine-Pitch Ball Grid Array (FBGA) 8.0 x 8.0 mm
NOTES: PACKAGE JEDEC DxE SYMBOL A A1 A2 D E D1 E1 MD ME n Ob eE eD SD / SE 0.25 NSC 133 N/A 8.00 mm x 8.00 mm PACKAGE MIN 0.90 0.20 0.70 NOM 1.00 0.25 0.76 8.00 BSC 8.00 BSC 6.50 BSC. 6.50 BSC. 14 14 133 0.30 0.50 BSC. 0.50 BSC 0.25 BSC. 0.35 MAX 1.10 0.30 0.82 PROFILE BALL HEIGHT BODY THICKNESS BODY SIZE BODY SIZE MATRIX FOOTPRINT MATRIX FOOTPRINT MATRIX SIZE D DIRECTION MATRIX SIZE E DIRECTION BALL COUNT BALL DIAMETER BALL PITCH BALL PITCH SOLDER BALL PLACEMENT 8. 9 6 7 4. 5. NOTE 2. 3. 1. DIMENSIONING AND TOLERANCING METHODS PER ASME Y14.5M-1994. ALL DIMENSIONS ARE IN MILLIMETERS. BALL POSITION DESIGNATION PER JESD 95-1 SPP-010. e REPRESENTS THE SOLDER BALL GRID PITCH. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D" DIRECTION. SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE "E" DIRECTION. n IS THE NUMBER OF POPULTED SOLDER BALL POSITIONS FOR MATRIX SIZE MD X ME. DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL DIAMETER IN A PLANE PARALLEL TO DATUM C. SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A AND B AND DEFINE THE POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW. WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE OUTER ROW SD OR SE = 0.000. WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW, SD OR SE = e/2 "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED BALLS. A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.
3583 \ 16-039.22 \ 8.15.06
D5-D11,E4-E11,F4-F11,G4-G11 DEPOPULATED SOLDER BALLS H4-H11,J4-J11,K4-K11,L4-L11
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Data
Sheet
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6.3
ALJ128--128-ball Fine-Pitch Ball Grid Array (FBGA) 12.0 x 12.0 mm
PIN A1 CORNER
D
9 INDEX MARK
A
D1 eD SD
7
A B C D E F G
PIN A1 CORNER
SE
7
E eE
0.10 C (2X)
18 17 16 15 14 13 12 11 10 9 8 76 5 4 3 2 1
H J K L M N P R T U V
E1
B
TOP VIEW
0.10 C (2X)
BOTTOM VIEW
A A2 A1
6
0.10 C
C
0.10 C
SIDE VIEW b
M C AB MC
128X
0.15 0.08
PACKAGE JEDEC DxE SYMBOL A A1 A2 D E D1 E1 MD ME n N R Ob eE eD SE / SD 0.40
ALJ 128 N/A 12.00 mm x 12.00 mm PACKAGE MIN --0.35 0.60 NOM ------12.00 BSC. 12.00 BSC. 11.05 BSC. 11.05 BSC. 18 18 128 128 2 0.45 0.65 BSC. 0.65 BSC 0.325 BSC.
C3~C16, D3~D16, E3~E16, F3~F16 G3~G16, H3~H16, J3~J16, K3~K16 L3~L16, M3~M16, N3~N16, P3~P16 R3~R16, T3~T16
NOTES: 1. 2. NOTE PROFILE BALL HEIGHT BODY THICKNESS BODY SIZE BODY SIZE MATRIX FOOTPRINT MATRIX FOOTPRINT MATRIX SIZE D DIRECTION MATRIX SIZE E DIRECTION BALL COUNT MAXIMUM NUMBER OF BALLS NUMBER OF LAND PERIMETERS 0.50 BALL DIAMETER BALL PITCH BALL PITCH SOLDER BALL PLACEMENT DEPOPULATED SOLDER BALLS 8. 9 7 6 3. 4. 5. DIMENSIONING AND TOLERANCING METHODS PER ASME Y14.5M-1994. ALL DIMENSIONS ARE IN MILLIMETERS. BALL POSITION DESIGNATION PER JEP95, SECTION 3.0, SPP-010. e REPRESENTS THE SOLDER BALL GRID PITCH. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D" DIRECTION. SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE "E" DIRECTION. n IS THE NUMBER OF POPULTED SOLDER BALL POSITIONS FOR MATRIX SIZE MD X ME. N IS THE MAXIMUM NUMBER OF BALLS ON THE FBGA PACKAGE. DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL DIAMETER IN A PLANE PARALLEL TO DATUM C. DATUM C IS THE SEATING PLANE AND IS DEFINED BY THE CROWNS OF THE SOLDER BALLS. SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A AND B AND DEFINE THE POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW. WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE OUTER ROW SD OR SE = 0.000. WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW, SD OR SE = e/2 "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED BALLS. A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.
3561 16 038 24 \ 5 15 6
MAX 1.15 --0.72
10 OUTLINE AND DIMENSIONS PER CUSTOMER REQUIREMENT.
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6.4
ASF128--128-ball Fine-Pitch Ball Grid Array (FBGA) 12.0 x 12.0 mm
PACKAGE JEDEC DxE SYMBOL A A1 A2 D E D1 E1 MD ME n N R Ob eE eD SE / SD 0.40
ASF128 N/A 12.00 mm x 12.00 mm PACKAGE MIN 0.95 0.35 0.59 NOM 1.05 0.40 --12.00 BSC. 12.00 BSC. 11.05 BSC. 11.05 BSC. 18 18 128 128 2 0.45 0.65 BSC. 0.65 BSC 0.325 BSC. C3-C16,D3-D16,E3-E16, F3-F16,G3-G16,H3-H16, J3-J16,K3-K16,L3-L16, M3-M16,N3-N16,P3-P16, R3-R16,T3-T16 0.50 MAX 1.15 0.45 0.72 PROFILE BALL HEIGHT BODY THICKNESS BODY SIZE BODY SIZE MATRIX FOOTPRINT MATRIX FOOTPRINT MATRIX SIZE D DIRECTION MATRIX SIZE E DIRECTION BALL COUNT MAXIMUM NUMBER OF BALLS NUMBER OF LAND PERIMETERS BALL DIAMETER BALL PITCH BALL PITCH SOLDER BALL PLACEMENT DEPOPULATED SOLDER BALLS NOTE
NOTES: 1. 2. 3. 4. 5. DIMENSIONING AND TOLERANCING METHODS PER ASME Y14.5M-1994. ALL DIMENSIONS ARE IN MILLIMETERS. BALL POSITION DESIGNATION PER JEP95, SECTION 3.0, SPP-010. e REPRESENTS THE SOLDER BALL GRID PITCH. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D" DIRECTION. SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE "E" DIRECTION. n IS THE NUMBER OF POPULTED SOLDER BALL POSITIONS FOR MATRIX SIZE MD X ME. N IS THE MAXIMUM NUMBER OF BALLS ON THE FBGA PACKAGE. 6 DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL DIAMETER IN A PLANE PARALLEL TO DATUM C. DATUM C IS THE SEATING PLANE AND IS DEFINED BY THE CROWNS OF THE SOLDER BALLS. 7 SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A AND B AND DEFINE THE POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW. WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE OUTER ROW SD OR SE = 0.000. WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW, SD OR SE = e/2 8. 9 "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED BALLS. A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.
3581\16-039.24\8.3.6
10 OUTLINE AND DIMENSIONS PER CUSTOMER REQUIREMENT.
S72NS-P_00_01 September 6, 2006
S72NS-P Based MCPs/PoPs
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Data
Sheet
(Advance
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7.
7.1
Revision History
Revision 01 (September 6, 2006)
Initial release.
Colophon The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for any use where chance of failure is intolerable (i.e., submersible repeater and artificial satellite). Please note that Spansion will not be liable to you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country, the prior authorization by the respective government entity will be required for export of those products. Trademarks and Notice The contents of this document are subject to change without notice. This document may contain information on a Spansion product under development by Spansion. Spansion reserves the right to change or discontinue work on any product without notice. The information in this document is provided as is without warranty or guarantee of any kind as to its accuracy, completeness, operability, fitness for particular purpose, merchantability, non-infringement of third-party rights, or any other warranty, express, implied, or statutory. Spansion assumes no liability for any damages of any kind arising out of the use of the information in this document. Copyright (c) 2006 Spansion Inc. All Rights Reserved. Spansion, the Spansion logo, MirrorBit, ORNAND, and combinations thereof are trademarks of Spansion Inc. Other names are for informational purposes only and may be trademarks of their respective owners.
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S72NS-P Based MCPs/PoPs
S72NS-P_00_01 September 6, 2006

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